Computing devices and systems contain components (such as circuit boards) as well as interconnects and interfaces between various components. During design of such systems, and prior to distribution to consumers, these interconnects may be tested to determine their proper functionality. However, as component to component bus speeds increase and circuit boards become smaller, testing these bus connections becomes increasingly difficult and in some cases impossible.
Board level features such as in-circuit testpoints have been eliminated on high performance buses (i.e., speeds greater than 200 MHz.) due to board/component electrical issues. As bus speeds increase beyond 500 MHz., additional testability features such as boundary scan may also be reduced and/or eliminated due to restricted timing budgets. Further, the board/system interconnect fault spectrum associated with high speed system buses has expanded beyond simple opens/shorts due to limited tolerance to transmission line loss, impedance discontinuities, return path discontinuities, intersymbol interferences (ISI), crosstalk, power supply collapse, nonlinear driver effects, non-optimum VOH, VOL levels, non-ideal termination and uncentered Vref, for example.
Testing processes may be employed to address the associated interconnect fault spectrum. One test process may use a system level environment (board functional test) incorporating a significant amount of hardware to accomplish the testing in a high volume manufacturing (HVM) test environment. This may be expensive and time consuming. Additionally, this type of testing may not provide full coverage and may have poor diagnostic granularity. Also, a majority of defective components may fail to boot an operating system and thus testing can not be accomplished. Another process may use physical access such as probing to test points (i.e., in-circuit testers) on the board. However, the probing may be invasive to high speed bus testing, expensive and/or obsolete for buses operating above 200 MHz.